The present invention relates to a method of partitioning specifications and functions required in designing a semiconductor integrated circuit device between hardware implementation and software implementation.
It is conventionally significant to determine, in design of a semiconductor integrated circuit device, which part of specifications and functions required for the system is implemented by software and which part is implemented by hardware. This is because significant characteristics such as the power consumption, the layout area and the throughput are affected depending upon how they are partitioned between software implementation and hardware implementation.
In design of a semiconductor integrated circuit device, a designer appropriately partitions the specifications and functions required for the system between hardware implementation and software implementation in consideration of developing process techniques, circuit techniques and device characteristics. Thus, the partitioning is currently entrusted to the skill of a designer.
Since the scale of a semiconductor integrated circuit device to be designed is enlarging and a large scaled system designated as a system LSI is desired to be constructed, it is difficult to improve the design efficiency merely by relaying upon the skill of a designer.
Accordingly, a technique for automatic partitioning between hardware implementation and software implementation is desired in the design of a semiconductor integrated circuit device. There remain, however, a number of unsolved problems in how the partitioning is automated with stress laid on which characteristic.
An object of the invention is realizing automatic partitioning between software implementation and hardware implementation by using a processing quantity and power consumption as parameters, generating an interface between hardware and software necessary in the partitioning and providing further means for increasing a processing speed and reducing power consumption.
The first method of designing a semiconductor integrated circuit device of this invention comprises the steps of (a) extracting description parts describing a loop processing part or a function by analyzing a system operation description language describing operations of the semiconductor integrated circuit device to be designed; (b) partitioning each of the description parts extracted from the system operation description language into a H/W implemented description when a processing quantity corresponding to a number of clock cycles of the description part exceeds a threshold value and into a S/W implemented description when the processing quantity is smaller than the threshold value; (c) calculating a sum of the processing quantities of the description parts as a total processing quantity; and (d) determining whether or not the calculated total processing quantity meets a condition.
According to this method, appropriate S/W and H/W partitioning can be automatically conducted with appropriately keeping the total processing quantity of the semiconductor integrated circuit device. In particular, by initially setting not only the condition but also a threshold value of a processing quantity of a description part to be implemented by H/W, it is possible to avoid a problem that a layout area and power consumption are too large due to too many H/W implemented description parts. In this method, simulation may be conducted, but the S/W and H/W partitioning can be carried out by checking the contents of the description parts of the system operation description language through a source code analysis without conducting simulation.
The first method can further comprise a step (e) of converting a description of one of the description parts and returning to the step (c) when the total processing quantity does not meet the condition in step (d), so that the step (e) can be repeatedly conducted until the total processing quantity meets the condition. In this manner, a constraint derived from the threshold value can be gradually eased, so as to design a semiconductor integrated circuit device satisfying the desired condition.
Furthermore, when the total processing quantity does not meet the condition after conducting the step (e) on all of the description parts, a procedure can return to the step (b) after easing the condition. In this manner, a state where the design is impossible because of an unreasonable condition can be avoided.
The threshold value can be given as a number of condition divergences appearing in the description part.
Also, the condition can be a desired range or an upper limit of the total processing quantity.
The first method of designing a semiconductor integrated circuit device can further comprise a step of obtaining total power consumption on the basis of all of the description parts partitioned between the H/W implemented description and the S/W implemented description, and when the total power consumption does not meet a condition, a procedure can return to the step (c) after converting a description of one of the description parts. In this manner, the S/W and H/W partitioning can be conducted also in consideration of power consumption.
The second method of designing a semiconductor integrated circuit device of this invention comprises the steps of (a) obtaining power consumption of each function by analyzing functions included in a system operation description language describing operations of the semiconductor integrated circuit device to be designed; (b) partitioning the function into a H/W implemented function when the power consumption of the function exceeds a threshold value and into a S/W implemented function when the power consumption is smaller than the threshold value; (c) calculating a sum of the power consumption of all of the functions as total power consumption by estimating the power consumption of each function; and (d) determining whether or not the calculated total power consumption meets a condition.
According to this method, the S/W and H/W partitioning for reducing power consumption can be automatically conducted. Accordingly, the efficiency in designing an LSI with small power consumption and the performance of the semiconductor integrated circuit device to be designed can be both improved.
In the second method, at least a use frequency of a general operation instruction in the function can be analyzed in the step (c), and the threshold value can be a value corresponding to an effect to reduce power consumption attained by H/W implementation of the function.
Alternatively, at least an invoke frequency of the function can be analyzed in the step (c), and the threshold value can be a value obtained by partitioning a value corresponding to an effect to reduce power consumption attained by H/W implementation of the function by a smallest processing quantity among processing quantities of the functions.
When the total power consumption does not meet the condition in the step (d), the step (c) can be repeatedly conducted after reducing the threshold value.
Furthermore, probability of increase of an operation speed through H/W implementation can be further analyzed in the step (c), and when throughput attained after increasing the operation speed is larger than throughput attained before increasing the operation speed, the function can be implemented by H/W. In this manner, a semiconductor integrated circuit device with large throughput can be designed in consideration of probability of employment of parallel processing and pipeline processing.
In this method, power optimization can be conducted in the step (c) by at least one of reduction of an operation frequency of each function, use of gated clock, reduction of a supply voltage and bus coding.
Furthermore, when the condition of the step (d) is that a value obtained by multiplying a processing quantity of the function attained through H/W implementation by power consumption of a unit process of a processor is larger than power consumption of the function attained through H/W implementation, the effect to reduce power consumption can be definitely attained.
The second method can further comprise a step of obtaining a total processing quantity as a sum of processing quantities of all of the functions partitioned between the H/W implemented function and the S/W implemented function, and when the total processing quantity does not meet a condition, a procedure can return to the step (b) after converting a description of one of the functions. In this manner, a state where the design is impossible can be avoided.
The third method of designing a semiconductor integrated circuit device of this invention comprises the steps of (a) inputting a system operation description language describing operations of the semiconductor integrated circuit device to be designed and partitioning the system operation description language into respective elements; (b) detecting plural elements including a common process flow by analyzing the respective elements; (c) integrating the plural elements including the common process flow into a single element; and (d) partitioning the respective elements into a H/W implemented element and a S/W implemented element in accordance with characteristics thereof after the step (c).
The third method can further comprise, after the step (d), a step of determining whether or not the H/W implemented element and the S/W implemented element meet a condition, and when a result of determination is negative, a procedure can return to the step (c) for changing integration of the elements.
The method of this invention of analyzing power consumption of a circuit including at least a register, comprises the steps of (a) supplying a first source program including an instruction for repeating change between a first data and a second data N times, wherein N is a fixed natural number, for causing transition of a bit number in the register; (b) estimating power consumption through simulation of a circuit operation in accordance with the first source program and storing first power obtained as a result of estimation in storage means; (c) supplying a second source program including an instruction for repeating change between a third data and a fourth data N times for causing no bit transition in the register; (d) estimating power consumption through simulation of a circuit operation in accordance with the second source program and storing second power obtained as a result of estimation in the storage means; and (e) obtaining power consumed in causing the transition of the bit number in the register by dividing a difference between the first power and the second power by 2N.
In this manner, a power value required for data change in a register can be accurately analyzed with background noise eliminated.
The first apparatus for analyzing power consumption, functioning as an instruction set simulator, of this invention comprises test pattern generating means for generating a first source program including an instruction for repeating change between a first data and a second data N times, wherein N is a fixed natural number, for causing transition of a bit number in a register and a second source program including an instruction for repeating change between a third data and a fourth data N times for causing no bit transition in the transistor; and power analyzing means for receiving an output from the test pattern generating means, conducting simulation in accordance with the first and second source programs and analyzing power consumed in causing the transition of the bit number in the register.
The aforementioned effect can be attained also by this apparatus.
The second apparatus for analyzing power consumption, functioning as an instruction set simulator, of this invention comprises source program storing means for storing a source program consisting of plural processes including instructions; power information storing means for storing power information regarding power consumption of each of the instructions; and power analyzing means for conducting simulation by using the power information stored in the power information storing means in accordance with the source program and analyzing power consumed in executing the source program.
According to this apparatus, a process (instruction or register) with large power consumption can be rapidly detected in a circuit to be designed, so as to provide means for reducing power consumption.
The power information preferably includes information of power consumption in accordance with a bit transition number of a register.
The fourth method of this invention for a semiconductor integrated circuit device using an instruction set simulator, comprises the steps of (a) analyzing power consumption by conducting simulation in accordance with a source program consisting of plural processes including instructions by using the instruction set simulator; (b) obtaining power consumption of each process on the basis of a result of analysis of the power consumption of the step (a); (c) detecting, on the basis of power consumption of the respective processes obtained in the step (b), a specified process having power consumption larger than a threshold value; and (d) changing an instruction in the specified process into another instruction for reducing power consumption with keeping a result of the specified process.
According to this method, power consumption can be easily reduced by design change. In particular, by previously setting a threshold value, a process whose power consumption can be reduced is easily detected, and the power consumption can be reduced by automatic change of an instruction.
The fourth method further comprises a step of generating power information regarding power consumption of each of the respective processes, and power consumption of the specified instruction changed in the step (d) can be registered in the power information as an abnormality informing value. In this manner, the simulator is informed of a H/M implemented process, and the actual power consumption of the process is calculated by automatic simulation or the like.
The fifth method of designing a semiconductor integrated circuit device of this invention comprises the steps of (a) inputting a system operation description language describing operations of the semiconductor integrated circuit device to be designed; (b) inputting partitioning information including information used for S/W and H/W partitioning of respective operation descriptions of the system operation description language; (c) partitioning the respective operation descriptions of the system operation description language between a H/W implemented operation description and a S/W implemented operation description on the basis of the partitioning information; and (d) automatically generating an interface between S/W and H/W.
According to this method, an interface for smoothly controlling data input/output between a S/W implemented part and a H/W implemented part and controlling the operation of the H/W implemented part by the S/W implemented part can be automatically generated in the S/W and H/W partitioning. Therefore, the design efficiency and the quality of the semiconductor integrated circuit device to be designed can be both improved.
The fifth method can further comprise, after the step (d), a step of adding the interface between S/W and H/W to the S/W implemented operation description.
In the fifth method, a database including information used for generating the interface between S/W and H/W can be previously prepared, the method can further include a step of extracting a description regarding data input/output of H/W and a description regarding an operation of a processor from the S/W implemented operation description and the H/W implemented operation description partitioned in the step (c), and the interface between S/W and H/W generated in the step (d) can include a description regarding data input/output between the processor and the H/W and a description regarding determination of termination of a process of the H/W.
The fifth method can further comprise, after the step (d), a step of adding the interface between S/W and H/W to the H/W implemented operation description.
Furthermore, in the fifth method, a database including information used for generating the interface between S/W and H/W can be previously prepared, the method can further include a step of extracting a description regarding data input/output of H/W and a description regarding an operation of a processor from the S/W implemented operation description and the H/W implemented operation description partitioned in the step (c), and an interface peripheral circuit operation description for operating H/W generated by the. H/W implemented operation description can be generated in the step (d).